1. Field of the Invention
The present invention relates to an electronic semiconductor device and method of fabrication, particularly to voltage threshold adjustment for field effect transistors (FETs), and more particularly to the combination of geometry and multiple gate materials used to establish a total work function for a predetermined threshold voltage during gate fabrication.
2. Description of Related Art
The voltage threshold for a field effect transistor, for example a metal-oxide-semiconductor (MOSFET), is the gate voltage necessary to initiate conduction. Generally, a FET has a significant disadvantage in that the threshold voltage, VT, usually varies with respect to geometry, the channel length L, and the drain bias. In a polysilicon gate FET, the type of doping in the polysilicon of the gate electrode has a large influence on the threshold voltage. The polysilicon is typically heavily doped to achieve low resistivity. The Fermi energy of heavily doped (n-type) polysilicon is close to the energy at the edge of the conduction band of silicon. The work function of a material is the difference between the vacuum energy level and the Fermi energy level of the material. In general, the positive gate voltage of an n-channel device must be larger than some threshold voltage before a conducting channel can be induced. Similarly, the negative gate voltage of a p-channel device must be more negative than some threshold voltage to induce the required positive charge in the channel.
As gate lengths scale below 50 nm, FET scaling becomes limited by the finite depth of the gate control. As the channel length, L, decreases, there is a considerable problem with a diminishing threshold voltage, VT. This effect severely impairs device performance and makes it difficult to design integrated circuits with short channel lengths. This problem with threshold voltage control is not apparent until the channel length approaches submicron levels.
As very large scale integration (VLSI) processes are used to make FETs, the channel lengths become shorter and the gate oxides become thinner, and a higher doping level under the gate in the channel region is required to provide the desired threshold and subthreshold voltage characteristics. However, dopant diffusion from a gate electrode into an underlying channel region may affect the device parameters of the FET, including the threshold voltage.
Some resolutions to this problem include adjusting the threshold voltage by diffusion, doping polysilicon to different conductivity types, and modifying the gate work function difference. For example, in U.S. Pat. No. 4,786,611 issued to Pfiester on Nov. 22, 1988, entitled, xe2x80x9cADJUSTING THRESHOLD VOLTAGES BY DIFFUSION THROUGH REFRACTORY METAL SILICIDES,xe2x80x9d a method for adjusting threshold voltages by diffusing impurities is taught. This adjustment is made relatively late in the fabrication process. A masking step selectively provides blocking elements to prevent the diffusion from occurring in certain FETs.
In U.S. Pat. No. 5,933,721 issued to Hause, et al., on Aug. 3, 1999, entitled, xe2x80x9cMETHOD FOR FABRICATING DIFFERENTIAL THRESHOLD VOLTAGE TRANSISTOR PAIR,xe2x80x9d a dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors.
In U.S. Pat. No. 5,942,786 issued to Sheu, et al., on Aug. 24, 1999, entitled, xe2x80x9cVARIABLE WORK FUNCTION TRANSISTOR HIGH DENSITY MASK ROM,xe2x80x9d a work function of the gates is selected for each potential transistor, which, in turn, selects the threshold voltage for the transistor. P-type and n-type polysilicon are the different work function materials used as gate materials to selectively produce transistors having different threshold voltages. However, each gate material type is dedicated to a single transistor. No attempt is made to combine different gate materials having different work functions for altering the threshold voltage of an individual transistor. Nor is any attempt made to pattern the geometry of this gate material to accommodate shorter channel lengths and different threshold voltage values for individual transistors on the same wafer using a plurality of gate materials.
By placing gates on multi-sides of the FET channel, numerous researchers have theoretically and experimentally shown improvements in FET performance. As miniaturization continues, the supply voltages are required to be smaller. Thus, the magnitude of the threshold voltage must also decrease. Current designs require a thin channel region, tsi, on the order of 5-50 nm with gate lengths down to 20-200 nm, and Lg approximately equal to 2-4 times tsi. 
For the double-gate FETs where a very thin ( less than 10 nm) silicon channel is utilized, it is possible and desirable to use an undoped silicon channel. However, the threshold voltage of such an FET would be entirely determined by its geometry and the work function of the gate material. It is often desirable to provide a variety of threshold voltages on the same chip for optimal circuit design. The present invention focuses on providing multiple threshold voltages on the same chip. The multiple threshold voltages are provided by different work functions of the gate materials and, importantly, by placing specific geometric restrictions on these materials in their layout to accommodate having these multiple threshold voltages on the same wafer.
Reported techniques for generating a dual-gated structure include simply defining the gate lithographically with high step heights, selective epitaxial growth to form an xe2x80x9cair-bridgexe2x80x9d silicon structure, and wrap-around gates with vertical carrier transport. However, introducing multiple threshold voltages on the same wafer for very large scale integrated circuit chips requires a defined geometry of predetermined gate materials in close proximity to one another.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for providing a variety of threshold voltages on the same integrated circuit chip for optimal circuit design that allows for an undoped or lightly doped silicon channel.
It is another object of the present invention to provide a FET and method of making the same that minimizes the silicon channel thickness and the adverse effects of diffusion of high dopant materials.
A further object of the invention is to provide a FET and method of making the same that maintains a geometric relationship between each channel and the work functions or gate materials necessary to establish a threshold voltage.
Yet another object of the present invention is to provide a FET and method of making the same that achieves the desired threshold voltage for thin channel devices, such as those used in VLSI chips.
Still other advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a FET comprising: a multilayer substrate having a top surface; electrically coupled source regions and electrically coupled drain regions in the substrate; a channel region in the substrate between the source and the drain regions, having a plurality of gate regions there through for controlling current flow through the channel region, the gate regions each comprising a different gate material having an associated work function for the FET; and, the plurality of gate regions situated in a predetermined geometric pattern such that the different gate materials are adjacent to each other.
The multilayer substrate may further comprise: electrical contacts connected to the gate material, the contacts isolated by a silicide layer, a nitride layer, and an oxide layer; and, a boron phosphorous glass isolation layer.
The predetermined geometric pattern comprises a linear array of the plurality of gate regions having the different gate materials in close proximity to each other. Some of the associated work functions of the plurality of different gate materials are combined to form a first total work function, and others of the associated work functions are combined to form a second total work function different from the first total work function.
In a second aspect, the present invention is directed to an integrated circuit chip having a plurality of field effect transistors therein, the transistors having narrow channel thickness and different threshold voltages, the threshold voltages determined by combination and adjacent positioning of at least two different gate materials, wherein the gate materials represent at least two different work functions.
At least two different work functions are averaged to form one total work function for one of the plurality of field effect transistors. The integrated circuit chip further comprises placing the at least two different gate materials in a geometric pattern such that each of the different gate materials are adjacent and physically close to one another for the combination.
Each of the field effect transistors includes: a source region; a drain region electrically coupled to the source region; and, a channel region between the source region and the drain region having the at least two gate regions there through for controlling current flow through the channel region.
The geometric pattern comprises an array of the at least two different gate materials; the array having rows and columns of the different gate materials such that each of the different gate materials is adjacent to the other gate materials.
In a third aspect, the present invention relates to a method of fabricating a field effect transistor comprising the steps of: providing a substrate having a source layer thereon; forming a channel layer on the source layer; forming a drain layer on the channel layer; forming gate trenches through the channel and drain layers; forming a gate oxide layer in the gate trenches; disposing in at least one of the gate trenches a first gate material having a first work function, the first gate material for controlling a current flow through the channel layer in response to a voltage of the first gate material; and, disposing in at least another one of the gate trenches a second gate material having a second work function, the second gate material for controlling current flow through the channel layer in response to a voltage of the second gate material.
The method further includes aligning the first and second gate materials in close proximity to one another and combining the first and second work functions to form a threshold voltage different from the voltage of the first gate material and different from the voltage of the second gate material. Aligning further comprises placing the first and second gate materials in a linear array of rows and columns such that the first and second gate materials are adjacent to one another in each of the rows and columns.
In a fourth aspect, the present invention relates to a method of making field effect transistors on a wafer having a plurality of predetermined threshold voltages, comprising: providing a substrate having a top surface, an epitaxial layer, and pad film thereon; applying a source layer having a top surface to the pad film; applying a channel layer to the source layer; applying a drain layer to the channel layer; providing at least one isolation film to the drain layer; forming trenches through the layers down to the source layer top surface; expanding the trenches; oxidizing the wafer; etching the trench to be within the source layer and below the source layer top surface; providing a dummy filler to the trench; polishing the dummy filler to be coplanar with the isolation film; removing the dummy filler; masking the wafer to apply at least two different gate materials to the trenches; applying low resistance material to the at least two different gate materials to form an electrical contact; combining the at least two different gate materials to form a total work function for one of the predetermined threshold voltages; and, providing a final isolation barrier to the wafer leaving the electrical contact accessible for connection. The source layer may comprise highly doped silicon, and the channel layer may comprise silicon having a doping concentration less than the source layer. The drain layer may comprise silicon having a doping concentration greater than the channel layer. Forming the trenches further comprises aligning the trenches in a predetermined geometric pattern such that the trenches are in close proximity to one another. Masking the wafer to apply at least two different gate materials to the trenches further comprises aligning the mask in a predetermined geometry such that the different gate materials can be applied adjacent to one another. The method further comprises: striping the isolation film; etching a space surrounding the electrical contact; and, applying a spacer nitride layer, a silicide layer, and an oxide fill layer.